A technology for integrated circuits must be judged on at least two criteria besides the obvious need for practicality of fabrication. The devices should be densely packed on the integrated circuit to allow a large number of individual devices on a small area chip. Furthermore, the devices must be fast so that the integrated circuit has a high throughput. The speed of most technologies is limited by stray capacitance, both between devices and to the substrate. Many recent designs, such as those disclosed by Rao in U.S. Pat. No. 4,388,121 and by Koomen et al in U.S. Pat. No. 4,317,690, have attempted to reduce the area by using multi-layer structures so that two separate elements are occupying the same surface area and no area is occupied by their interconnects. This approach, however, introduces capacitance between the layers. Furthermore, these devices are usually built on a semiconductor substrate so that there is an unavoidable capacitance to the substrate. It should be noted that, in some situations, a high capacitance is desired, such as in dynamic memory cells. If the capacitance per area of the memory cell can be increased, the total area of the memory cell can be decreased, resulting in a high chip density. A further advantage of high capacitance for small area memory cells is the immunity to alpha particles. Thus, it is desirable to simultaneously have low capacitance and high capacitance areas on the same integrated circuit.
One technology that eliminates substrate capacitance is silicon on sapphire (SOS). In SOS, a layer of silicon is grown on top of an insulating sapphire substrate. As a result, substrate capacitance is negligible. However, SOS tends to require fairly large surface areas and multi-layer SOS devices are not common.
A recent variant of SOS is silicon on insulator (SOI), in which a silicon layer is formed on top of a layer of silicon dioxide. A description of SOI technology is contained in a technical article by A. Jastrzebski, appearing in the RCA Review, Vol. 44, June 1983 at pp.250-269 and entitled "Comparison of Different SOI Technologies: Assets and Liabilities".